The present invention relates to the use of thin film deposition technology to create high density interconnects on a conventional printed wiring board substrate. More specifically, the present invention pertains to an improved method for testing for open circuits between high density connections in the overlying deposited thin film layers and low density connections that are either internal to the substrate or on the bottom of the substrate. The method of the present invention can be used with or without conventional build-up layers and initial conventional build-up layers and is useful for high density integrated circuit packaging of single chip, multi-chip, and support components such as resistors and capacitors. The method of the present invention is also useful for creating interconnections on high density daughter boards that carry packaged devices.
The semiconductor industry continues to produce integrated circuits of increasing complexity and increasing density. The increased complexity of some of these integrated circuits has in turn resulted in an increased number of input/output pads on the circuit chips. At the same time, the increased density of the chips has driven the input/output pad pitch downward. The combination of these two trends has been a significant increase in the connector pin wiring density needed to connect the chips to packages that interface with the outside world and interconnect the chips to other integrated circuit devices.
A number of different technologies have been developed to interconnect one or more integrated circuits and related components. One such technology is based on traditional printed wiring board (PWB) technology that found wide use during the period in which integrated circuits were packaged in surface mount devices like quad flat packs (QFPs). When used to interconnect multiple integrated circuits this PWB technology is often referred to as MCM-L or laminate MCM technology. PWB technology typically uses copper and insulating dielectric material sub-laminates as building blocks to create the required interconnect structures. The process of forming a copper conductive pattern on the sub-laminate in PWB technology typically includes forming a dry film of photo resist over the copper layer, patterning and developing the photo resist to from an appropriate mask and selectively etching away the unwanted copper thereby leaving the desired patterned conductive layer.
Substrates used in PWB technology can be manufactured in large area panels providing efficiencies that lower the costs of production. Interconnect solutions using this technology generally have relatively good performance characteristics because of the copper and low dielectric constant (e.g. less than or equal to 4.0) employed. The printed wiring board industry, however, has not kept pace with the advances in semiconductor manufacturing in terms of pad density and pad count. As a result, there is a capability gap between semiconductor manufacturers and interconnect printed wiring board manufactures.
In some applications, two or more pieces of laminate are laminated together to form a final structure. Interconnection between laminated layers can be provided by through hole mechanical drilling, followed by plating. The drilling process is relatively slow and expensive and can require a large amount of board space. As the number of interconnect pads increases, an increased number of signal layers is often used to form the interconnect structure. Because of these limitations, the conventional printed wiring board technology needs to go to a large number of metal layers (e.g. greater than eight layers) for some of the applications in high density integrated circuit packaging and daughter board fabrication. Utilizing a large number of layers in this context generally increases cost and decreases electrical performance. Also, the pad size limits the wiring density on any given layer with this technology. Thus, PWB technology, while useful for some applications, is not capable of providing the connection density required in other applications.
To improve the interconnect density of PWB technology, an advanced printed wiring board technology approach called build-up multi-layer has been developed. In this technology a traditional printed wiring board core is the starting point. Standard drilling and plating techniques are used to form plated through holes in the core. From the basic core this build-up approach has many variations. Typically a dielectric layer approximately 50 microns thick is laminated to both the top and bottom major surfaces of the conventionally fabricated printed wiring board substrate. Vias are made in the build-up layer by laser ablation, photo mask/plasma etch, or other known methods. An electroless seeding step is then done prior to a panel plating step that metalizes both the upper and lower surfaces. Subsequent masking and wet etching steps then define a desired conductive pattern over the laminated dielectric layers.
This technology offers a large improvement in terms of density over standard PWB technology without build-up layers; however, such build-up boards require multiple layers in order to meet the developing high density packaging and daughter board requirements. Thus this technology still has limitations.
Another conventional approach used to package high density interconnect applications uses cofired ceramic substrates and is referred to generally as multilayer ceramic or MLC technology or as MCM-C, cofired ceramic MCM and thick film MCM technology in the multichip module context. Basically, MLC technology involves rolling a ceramic mix into sheets, drying the sheets, punching vias, screening the rolled sheets with a metal paste representing the trace pattern on the surface of the ceramic, stacking and laminating all the layers together, then cofiring at a high temperature (e.g. greater than 850.degree. C.) to achieve the desired interconnections.
MLC construction has found extensive use in high density and high reliability products where the robustness of the high density interconnect package outweighs the cost considerations. The ability to create a hermetic seal in the ceramic improves the ability to withstand environments not tolerable to conventional printed wiring board technology. While this technology is capable of high density packaging applications (e.g. greater than 1000 pads), it is also very costly. Additionally, performance characteristics, such as signal propagation time, are impacted due to the relatively high dielectric constant (e.g. between 5.0 and 9.0) of the ceramic material. MLC technology provides higher connection density than PWB technology, but is not capable of providing the connection density required for some of today's high density interconnect applications.
A third approach which the high density interconnect and packaging industry has moved toward to address these high density interconnect applications uses thin film deposition technology and is sometimes referred to as deposited on laminate or DONL technology in a broad sense and as MCM-D or MCM deposition technology in a multichip module context. In some applications, such DONL technology includes forming and patterning thin film conductive traces over large substrates such as the laminated printed wiring boards discussed above. Such large substrates may have a surface area of 40 centimeters by 40 centimeters or more, thereby providing efficiencies that lower the costs of production.
DONL technology utilizes a combination of low cost printed wiring board structures, with or without the use of the build-up multi-layers on the printed wiring board, as a starting point to meet the high density and low cost interconnect requirements. This combination of existing conventional high volume printed wiring board technology and advanced thin film deposition technology represents a significant economic advantage and density improvement as compared to the previously discussed PWB and MLC technologies.
One significant feature of DONL technology is that it creates a high interconnect density substrate using thin film processes on only one side of the printed wiring board. The high density interconnects are formed by depositing alternating conducting and insulating thin film layers. The total thickness of several of these deposited layers is less than the thickness of a single traditional build-up layer. This eliminates the need for balancing the build-up layers on both top and bottom to prevent warpage of the substrate.
The DONL process involves first laying down a layer of an insulating dielectric on the top surface of a printed wiring board substrate, depositing a conductive material over the dielectric layer, creating a circuit pattern in the conductive material, then depositing the next insulating and conductive layers. The various layers so created are connected through vias constructed using a variety of known techniques such as wet chemical etch, photo expose and develop or laser ablation. In this way a three dimensional deposited laminated structure is achieved enabling high density interconnect patterns to be fabricated in small physical areas.
Despite the definite advantages of DONL technology, there are potential problems that may result in failure modes and performance limitations if the overlying deposited thin film layers and the underlying printed wiring substrate are not properly fabricated. One such problem encountered in fabrication is the formation of non-continuities between the high density connections in the top pad layer of the deposited thin film layers and the low density connections either internal to the substrate or on the bottom of the substrate.
Non-continuities, also known as open circuits, have multiple causes including cracking and breaking of the conductors from thermal stress, incomplete metal plating of the through holes, point defects and/or over developing or over etching of the conductive layers, or open interlayer vias. Irrespective of the source of the open circuit, the substrate cannot be used when this type of failure exists. Thus prior to placing and connecting components on the substrate a test is done to verify that all electrical connections to the substrate have been properly made.
One conventional method of testing the continuity of the substrate involves contact testing using automated or semi-automated test equipment. These devices rely on making physical contact with each of the top and bottom surface connection points, applying a current, usually under the control of a computer or automated tester, and displaying or logging the results for human analysis. Many contemporary testers provide a simple pass/fail indication.
The major types of contact testing currently employed include bed-of-nails testing combined with planar probe testing or a flying head tester. In a bed-of-nails tester the substrate is placed in a fixture and spring loaded probes, or nails, are positioned in physical contact with each net to be tested. The spring force must be carefully controlled in order to insure that no damage is done to the conductor being tested. It is also important to insure that the nails make and break contact without sliding laterally across the metal nets since such a motion may cause damage such as shorts and opens. In a typical installation, when the nails are all in place the computer will run its program and either display or log the results, or both. A human operator then interprets the results and takes appropriate action. Another approach is a combination of both to speed up the process.
In planar probe testing, the substrate is again mounted in a fixture but instead of nails a series of relatively delicate probes, which have been planarized to make contact at exactly the same time, are placed on the surface of the substrate. This method uses less tactile force and has a finer probe contact pitch than bed-of-nails testing. Since the probes are rather delicate, however, they can be damaged by repeated contact with the surface of the substrate or by lateral motion during make/break sequences. Replacing and re-planarizing the probes is a time consuming and costly process.
Testing the continuity of substrates with thin film layers presents additional challenges to conventional test methods due to both the fine pitch of the connections and the delicate nature of the layers. With metalization and dielectric layers often less than 10 microns thick, the thin-film interconnect structure can be easily damaged by impact or sheer stresses generated by nails and probes. This delicate characteristic of the thin film layers increases the cost of the equipment, the set-up time, and the test time needed. All of these increase the cost and slow production.
Either of the contact test methods suffers from a number of drawbacks. First, the equipment required is itself costly and requires costly skilled technicians to program and maintain the equipment. Second, the mechanics of high density interconnect substrates are such that very fine control of the probes, or nails is required in three axes: X, Y and Z. Due to the dimensions of the pads and surface of the DONL structure, small errors in the Z axis (vertical axis) from improper probe planarization or nail pressure can cause severe physical damage to the substrate. Third, this test method requires time to complete. Each substrate must be mounted to a test fixture, subjected to the test and the results noted. This time is costly in terms of manufacturing efficiency resulting in a more costly end product.
Accordingly, more accurate and less time consuming test methods are desirable for thin film DONL fabrication processes.